1. Technical Field
The present invention relates to a semiconductor device, and to a detection method for detecting the pulse width of a pulse signal generate in the semiconductor device.
2. Related Art
Explanation follows, with reference to FIG. 6, regarding a configuration and detection method for detecting a pulse width of a pulse signal (referred to below as an internal pulse signal) generated within a conventional semiconductor device, such as a semiconductor memory or the like.
As shown in FIG. 6, each chip of a semiconductor device is provided with a NAND circuit 30 input with an enable signal PLS_EN and an internal pulse signal PLS, and an inverter 31 that inverts the output from the NAND circuit 30. The signal output from the inverter 31 is an internal pulse monitor signal PLSMON (note that while the NAND circuit 30 and the inverter 31 are given as an example of a circuit for outputting the PLSMON, an AND circuit may also be employed).
When the enable signal PLS_EN becomes “H” (enable: asserted), the internal pulse monitor signal PLSMON of the same waveform as that of the internal pulse signal PLS is output from the inverter 31, and the PLSMON is also output externally to the chip through the monitor driver 32 and the monitor pad 33 functioning as a repeater.
Consider a case in which a probe needle 34 is contacted to the monitor pad 33 for measuring the internal pulse signal PLS. When the PLS_EN=“H” (test mode), the waveform output to the monitor pad 33 is the waveform input through the probe needle 34, and is input through the probe card 35 to a tester comparator 36 for detecting a rise timing and a fall timing of the pulse signal. These timings are measured by the tester comparator 36 at the measurement point MEASP and the pulse width is derived based on these timings.
An example of a detection device is described in JP-A No. 2009-175052 for detecting the pulse width from the waveform at the measurement point MEASP. This device is equipped with: a first timing detection section for detecting a first change timing of the measured signal; a second timing detection section for detecting a second change timing of the measured signal; a buffer section for buffering data expressing the first change timing detected by the first timing detection section and data expressing the second change timing detected by the second timing detection section; and a computation section that imports the data expressing the first change timing and the second change timing from the buffer section and computes the difference in timing between the first change timing and the second change timing.
The above conventional technology suffers from the problem that, particularly when the internal pulse signal PLS is short, either the pulse width cannot be detected accurately or the test duration for accurately detecting the pulse increases.
FIG. 7 shows a waveform of each signal in a conventional method shown in FIG. 6. After the enable signal PLS_EN has changed from “L” to “H”, the generated internal pulse signal PLS is output as the internal pulse monitor signal PLSMON. The waveform of the internal pulse monitor signal PLSMON is then output, through the monitor driver 32, the monitor pad 33, and the probe card 35, and measured at the measurement point MEASP by the tester comparator 36. However, as shown in FIG. 6, a delay (waveform rounding) is generated in the waveform at the measurement point MEASP by output impedance of the monitor driver 32 (Rdr), wiring resistance and capacitance (Rpc, Cpc) of the probe card 35, and load (Cc) of the tester comparator 36 present upstream of the measurement point. The time constant τ=(Rdr+Rpc)×(Cpc+Cc).
As shown in FIG. 8, suppose the Rdr=50Ω, Rpc=10 mΩ, Cpc=80 pF, Cc=40 pF, and the pulse width of the internal pulse signal PLS=6 ns, then the time constant τ and the pulse width of the internal pulse signal PLS are of the same order of duration as each other. Since the internal pulse signal PLS falls off when the period of the time constant τ portion is still elapsing, the waveform at the measurement point MEASP only reaches 63.2% of the maximum voltage value VCC of the pulse signal.
Since at least the output impedance (Rdr) of the monitor driver 32 fluctuates due to transistor parameters, variation occurs in the amplitude of the waveform at the measurement point MEASP depending on the chip, as shown in FIG. 9. Suppose that a fixed determination point such as threshold value VOH/VOL is set for detecting the timing of the rise and fall of the pulse signals shown in FIG. 9, the possibility arises that different pulse width detection values will be detected depending on the chip even though the pulse width of the internal pulse signal PLS is actually the same 6 ns. Consequently, accurate pulse widths cannot be detected by this method.
In order to accurately measure the pulse width for individual chips, after measuring the amplitude (voltage values) of the waveform at the measurement point MEASP for each of the chips, individual determination levels need to be set (for example: for VOH=amplitude at MEASP −0.1V, VOL=0.1V), and the pulse width detected for each chip. However, a great deal of time is required for testing when serial processing each chip with such a method.
Note that in JP-A No. 2009-175052, while there is a description of a measurement method employed by the detection device (measurement device) external to the semiconductor device after the waveform has been imported, since delay of the above waveform occurs at the stage when the waveform is imported into the detection device, the technology described in JP-A No. 2009-175052 cannot solve the above problem.